Akida Pico capabilities
Note
These details are relevant to Akida Pico IP-based solutions.
For compatibility with multiple possible hardware backends downstream, CNN2SNN and the Akida simulator impose few constraints on layer dimensions. However, hardware does have limits in this respect, which will be checked at the stage of mapping a model to a specific device (real or virtual). This page details the limits for the Akida Pico IP.
Please refer to Akida Pico layers for layer descriptions.
Model structure
Input
Layer |
Input bitwidth |
Channels |
First |
8 |
<=256 |
First |
16 |
<=128 |
Intermediate |
8 |
<=256 |
For example:
Input configuration |
Packed size |
32-bit words |
Status |
3 × 8-bit |
24 bits |
1 |
Valid |
9 × 8-bit |
72 bits |
3 |
Mapping error, pad channels to 13-16 (4 words) |
3 × 16-bit |
48 bits |
2 |
Valid |
6 × 16-bit |
96 bits |
3 |
Mapping error, pad channels to 7-8 (4 words) |
Parameters
Stateful channels |
Output channels |
Subsample |
<=256, power of 2 |
<=256 |
<=4 |
Input dimensions
Channels |
Timesteps |
1 |
[3:128] |
Note
In addition to the limits above, the memory required by each layer (events, states, filters and time constants) is checked against the SRAM sizes of the target device at mapping time.